Silicon Labs /EFR32ZG23A010F512GM40 /RFECA1_S /PLAYBACKCTRL

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Interpret as PLAYBACKCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SINGLE)MODE 0 (START_TRIGGER)COND 0 (BIT1)DATAWIDTH

MODE=SINGLE, COND=START_TRIGGER, DATAWIDTH=BIT1

Description

No Description

Fields

MODE

Playback Mode

0 (SINGLE): Playback starts at BUF0_BASE and stops at BUF1_BASE + BUF1_LIMITOFFSET

1 (LOOP): Playback starts at BUF0_BASE and loops/wraps continuously until CTRL.MODE != PLAYBACK (this can be supported in single or double-buffer modes)

COND

Playback Condition

0 (START_TRIGGER): Playback event occurs at every start-trigger event

1 (TIMED): Playback event occurs based on rate defined in PLAYBACL_RATE_CTRL

DATAWIDTH

Playback Data Width

0 (BIT1): 1 bit

1 (BIT2): 2 bits

2 (BIT4): 4 bits

3 (BIT8): 8 bits

4 (BIT16): 16 bits

5 (BIT32): 32 bits

Links

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